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NB4L6254 2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
Description
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The NB4L6254 is a differential 2x2 clock switch and drives precisely aligned clock signals through its LVPECL fanout buffers. It employs a fully differential architecture with bipolar technology, offers superior digital signal characteristics, has very low clock output skew and supports clock frequencies from DC up to 3.0 GHz. The NB4L6254 is designed for the most demanding, skew critical differential clock distribution systems. Typical applications for the NB4L6254 are clock distribution, switching and data loopback systems of high-performance computer, networking and telecommunication systems, as well as on-board clocking of OC-3, OC-12 and OC-48 communication systems. In addition, the NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL fanout buffer. The NB4L6254 can be operated from a single 3.3 V or 2.5 V power supply.
Features
LQFP-32 FA SUFFIX CASE 873A
NB4L 6254 AWLYYWWG
A WL YY WW G
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
* * * * * * * * * * *
Maximum Clock Input Frequency, 3 GHz CLK0 Maximum Input Data Rate, 3 Gb/s CLK0 Differential LVPECL Inputs and Outputs Low Output Skew: 50 ps Maximum Output-to-Output Skew Synchronous Output Enable Eliminating Output Runt Pulse Generation and Metastability CLK1 Operating Range: Single 3.3 V or 2.5 V Supply CLK1 VCC = 2.375 V to 3.465 V LVCMOS Compatible Control Inputs SEL0 Packaged in LQFP-32 SEL1 Fully Differential Architecture -40C to 85C Ambient Operating Temperature OEA These are Pb-Free Devices* OEB
VCC 0
Bank A
1
QA0 QA0 QA1 QA1 QA2 QA2
VCC 0
Bank B
1
QB0 QB0 QB1 QB1 QB2 QB2
Figure 1. Functional Block Diagram
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
August, 2006 - Rev. 1
1
Publication Order Number: NB4L6254/D
NB4L6254
VCC GND OEA CLK0 CLK0 SEL0 GND VCC
24 QA2 QA2 VCC QA1 QA1 VCC QA0 QA0 25 26 27 28 29 30 31 32 1
23
22
21
20
19
18
17 16 15 14 13 QB2 QB2 VCC QB1 QB1 VCC QB0 QB0
LQFP-32
12 11 10 9
2
3
4
5
6
7
8
VCC
GND SEL1 CLK1 CLK1 OEB
GND
VCC
Figure 2. Pin Configuration (Top View) Table 1. PIN CONFIGURATION
Pin Name CLK0, CLK0 CLK1, CLK1 OEAb, OEB SEL0, SEL1 QA[0-2], QA[0-2] QB[0-2], QB[0-2] GND VCC I/O LVPECL Input LVPECL Input LVCMOS Input LVCMOS Input LVPECL Output Description Differential reference clock signal input 0. Differential reference clock signal input 1. Output Enable Clock Switch Select Differential LVPECL Clock Outputs, (banks A and B) Typically terminated with 50 W resistor to VCC - 2.0 V. Negative Supply Voltage Positive supply voltage. All VCC pins must be connected to the positive power supply for correct DC and AC operation.
Power Supply Power Supply
Table 2. FUNCTION TABLE
Control OEA Default 0 0 QA[0-2], QA[0-2] are active. Deassertion of OEA can be asynchronous to the reference clock without generation of output runt pulses QB[0-2], QB[0-2] are active. Deassertion of OEB can be asynchronous to the reference clock without generation of output runt pulses Refer to Table 3 1 QA[0-2] = L, QA[0-2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses QB[0-2] = L, QB[0-2] = H (outputs disabled). Assertion of OE can be asynchronous to the reference clock without generation of output runt pulses Refer to Table 3
OEB
0
SEL0, SEL1
00
Table 3. CLOCK SELECT CONTROL
SEL0 0 0 1 1 SEL1 0 1 0 1 CLK0 Routed To QA[0:2] and QB[0:2] - QA[0:2] QB[0:2] - QA[0:2] and QB[0:2] QB[0:2] QA[0:2] CLK1 Routed to Application Mode 1:6 Fanout of CLK0 1:6 Fanout of CLK1 Dual 1:3 Buffer Dual 1:3 Buffer (Crossed)
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Table 4. ATTRIBUTES
Characteristics Internal Input Pullup Resistor Internal Input Pulldown Resistor ESD Protection Latchup Immunity Cin, inputs Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. LQFP-32 Oxygen Index: 28 to 34 Human Body Model Machine Model Value 37.5 kW 75 kW > 2000 V > 200 V >200 mA 4.0 pF (TYP) Level 2 UL 94 V-0 @ 0.125 in 336
Table 5. MAXIMUM RATINGS (Note 2)
Symbol VCC VIN VOUT IIN Iout TA Tstg qJA qJC Tsol VTT Parameter Positive Power Supply DC Input Voltage DC Output Voltage DC Input Current LVPECL DC Output Current Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (Note 3) Thermal Resistance (Junction-to-Case) Wave Solder Output Termination Voltage Pb-Free 0 lfpm 500 lfpm 2S2P (Note 3) LQFP-32 LQFP-32 LQFP-32 Continuous Surge LQFP-32 Condition Condition Rating -0.3 v VCC v 3.6 -0.3 v VIN v VCC + 0.3 -0.3 v VOUT v VCC + 0.3 $20 $50 100 -40 to +85 -65 to +150 80 55 12 to 17 265 VCC - 2.0, TYP Unit V V V mA mA mA C C C/W C/W C/W C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 2. Maximum Ratings are those values beyond which device damage may occur. 3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power); MIL-SPEC 883E Method 1012.1.
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NB4L6254
Table 6. DC CHARACTERISTICS VCC = 2.375 V to 3.465 V, GND = 0 V, TA = -40C to +85C
Symbol POWER SUPPLY CURRENT IGND VOH Power Supply Current (Outputs Open) 60 85 mA Characteristic Min Typ Max Unit
LVPECL CLOCK OUTPUTS LVPECL Output HIGH Voltage (Notes 4, 5) VCC = 3.3 V VCC = 2.5 V VCC = 3.3 V VCC = 2.5 V VCC - 1145 2155 1355 VCC - 1945 1355 555 VCC - 1020 2280 1480 VCC - 1770 1530 730 VCC - 895 2405 1605 VCC - 1600 1700 900 mV
VOL
LVPECL Output LOW Voltage (Notes 4, 5)
mV
CLOCK INPUTS VPP VCMR VIH VIL IIH Dynamic Differential Input Voltage (Clock Inputs) Differential Cross-point Voltage (Clock Inputs) 0.1 1.0 1.3 VCC - 0.3 V V
LVCMOS CONTROL INPUTS Output HIGH Voltage (LVTTL/LVCMOS) Output LOW Voltage (LVTTL/LVCMOS) Input Current VIN = VCC or VIN = GND -100 2.0 0.8 +100 V V mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. LVPECL Outputs loaded with 50 W termination resistors to VTT = VCC - 2.0 V for proper operation. 5. LVPECL Output parameters vary 1:1 with VCC.
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Table 7. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V, GND = 0 V, TA = -40C to +85C (Note 6)
Symbol VINPP VCMR fIN VOUTPP Characteristic Differential Input Voltage (Peak-to-Peak) Differential Input Cross-Point Voltage (Clock Inputs) Clock Input Frequency Differential Output Output Voltage Amplitude (Peak-to-Peak) (Note 7) fO < 1.1 GHz fO < 2.5 GHz fO < 3.0 GHz Output Clock Frequency Range Propagation Delay CLKx to Qx (Differential Configuration) Within Device Output-to-Output Skew (Differential Configuration) Device-to-Device Skew Output Pulse Skew (Duty Cycle Skew) (Note 8) Output CLOCK Duty Cycle (DC Ref = 50%) (Note 9) tREF <100 MHz tREF < 800 MHz 49.4 45.2 0.3 50 2.5 T + tPD 3 T + tPD 130 Min 0.3 1.2 0 0.45 0.35 0.2 0 360 485 25 30 10 0.70 0.55 0.35 3.0 610 50 250 60 50.6 54.8 0.8 300 3.5 T + tPD 4 T + tPD Typ Max 1.3 VCC - 0.3 3.0 Unit V V GHz V
fCLKOUT tpd tskew
GHz ps ps
DCO tJIT tr, tf tPDL tPLD
% ps ps ns ns
CLOCK Random Jitter (RMS) (SEL0 0 SEL1) (Note 10) Output Rise/Fall Times (Note 11) CLKx / CLKx Output Disable Time, T = CLK period Output Enable Time, T = CLK period
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 6. LVPECL Outputs loaded with 50 W to VCC - 2.0V. 7. VOUTPP MIN = 0.1 V @ +85C, fO < 3.0 GHz. 8. Output Pulse Skew is the absolute difference of the propagation delay times: |tPLH - tPHL| 9. DCOMIN/MAX = 43.2%/59.2% @ +85C. 10. tJITMAX = 1.6 ps @ 85C, 3.0 V 11. Measured 20% to 80%
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NB4L6254
CLKX CLKX
50%
OEX QXn QXn tPDL (OEX to QXn) tPLD (OEX to QXn) Outputs Disabled
Figure 3. Output Disable / Enable Timing
VOUTPP, OUTPUT VOLTAGE AMPLITUDE (TYP)
800 700 600 500 400 300 200 100 0 0 1 2 fOUT, CLOCK OUTPUT FREQUENCY (GHz) 3
Figure 4. Output Voltage Amplitude (VOUTPP) versus Clock Output Frequency at Ambient Temperature (Typical)
Q Driver Device Q
Zo = 50 W
D Receiver Device
Zo = 50 W 50 W 50 W
D
VTT VTT = VCC - 2.0 V
Figure 5. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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NB4L6254
Example Configurations
CLK0 CLK1 3 System A SEL0 0 0 1 SEL0 SEL1 3 1 System B SEL1 0 1 0 1 Switch Configuration System Loopback Line Loopback Transmit/Receive Operation System and Line Loopback
APPLICATIONS INFORMATION
Maintaining Lowest Device Skew
Figure 6. 2 x 2 Clock Switch
SEL0 0 0 1 1
SEL1 0 1 0 1
Switch Configuration CLK0 Clocks System A and System B CLK1 Clocks System A and System B CLK0 Clocks System A and CLK1 Clocks System B CLK1 Clocks System B and CLK1 Clocks System A
The NB4L6254 guarantees low output-output bank skew at 50 ps and a part-to-part skew of 250 ps. To ensure low skew clock signals in the application, both outputs of any differential output pair need to be terminated identically, even if only one output is used. When fewer than all nine output pairs are used, identical termination of all output pairs within the output bank is recommended. If an entire output bank is not used, it is recommended to leave all of these outputs open and unterminated. This will reduce the device power consumption while maintaining minimum output skew.
Power Supply Bypassing
CLK0 CLK1
0 0
SEL0 SEL1
Figure 7. 1:6 Clock Fanout Buffer
The NB4L6254 is a mixed analog/digital product. The differential architecture of the NB4L6254 supports low noise signal operation at high frequencies. In order to maintain its superior signal quality all VCC pins should be bypassed by high-frequency ceramic capacitors connected to GND. If the spectral frequencies of the internally generated switching noise on the supply pins cross the series resonant port of an individual bypass capacitor, its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the noise bandwidth.
VCC
System-Tx
CLK0
QAn
Transmitter VCC 33...100 nF 0.1 nF NB4L6254
SEL0 SEL1 System-Rx QBn CLK1 Receiver
Figure 9. VCC Power Supply Bypass
Figure 8. Loopback Device ORDERING INFORMATION
Device NB4L6254FAG NB4L6254FAR2G Package LQFP-32 (Pb-Free) LQFP-32 (Pb-Free) Shipping 250 Units / Tray 2000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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NB4L6254
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
-T-, -U-, -Z- AE P V V1 DETAIL Y
BASE METAL
32
A1
A
25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U-
17
N 9 -Z- S
8X M_ 4X
S1
R
J
G -AB-
SEATING PLANE
DETAIL AD CE
SECTION AE-AE
-AC- 0.10 (0.004) AC 0.250 (0.010) H W X DETAIL AD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION.
K
Q_
GAUGE PLANE
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
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0.20 (0.008)
0.20 (0.008) AC T-U Z
EE EE EE
F
9
D
M
AC T-U Z
DETAIL Y
AE
NB4L6254
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NB4L6254/D

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